This invention relates to a semiconductor memory device such as a dynamic random-access memory (DRAM), more particularly to a semiconductor memory device with a built-in cache in which data can be stored for quick recall.
A DRAM has, among other circuits, an array of memory cells identified by row and column addresses, and a row of sense amplifiers. In read or write access, a row address is input, the memory cells in the addressed row are coupled to the sense amplifiers, and their data are amplified. Next a column address is input, and in read access for example, the amplified data for the addressed column are output to a data bus. Further column addresses may then be input to access the data of other columns in the same row. When such access ends, in a conventional DRAM, the sense amplifiers are disabled, and the data remain held only in the memory cell array.
A problem in the conventional DRAM is that before each access cycle, the sense amplifiers, and the bit lines that couple them to the memory cells, must be precharged by equalizing them to a certain potential. Furthermore, at the beginning of every cycle, the sense amplifiers must amplify the data in an entire row of memory cells. Substantial time is required for these operations, particularly in a large-scale memory with long bit lines, which have large intrinsic capacitances that must be charged and discharged. This severely limits the access speed of the device.
One possible solution to this problem is to retain data in the sense amplifiers by leaving them enabled at the end of an access cycle, thereby using the sense amplifiers as a cache. Then if the same row address is input again, the addressed data are immediately available from the sense amplifiers and do not have to be read from the memory cells. This scheme is particularly suited to a device in which the memory cell array is divided into multiple banks, and multiple rows of sense amplifiers are provided, permitting data from different banks to be cached in different sense amplifier rows.
The utility of this method is restricted, however, by the need to refresh data in DRAM memory cells periodically. Each time a refresh is carried out, the data being held in the relevant sense amplifiers are lost. The data are also lost if the device is placed in standby and the sense amplifiers are powered down.
Another problem is that each row of sense amplifiers can hold data for only a single row of memory cells. If access alternates between two rows in the same bank, for example, the above method confers no benefit.